Thermal stability of copper Through-Silicon Via barriers during IC processing

  title={Thermal stability of copper Through-Silicon Via barriers during IC processing},
  author={Yann Civale and Kristof Croes and Yuichi Miyamori and Sarasvathi Thangaraju and A. Redolfi and Annemie Van Ammel and Dimitrios Velenis and Vladimir Cherman and Paul Hendrickx and Geert Van der Plas and Andrew Cockburn and Virginie Gravey and Nirajan Kumar and Zhitao Cao and Deniz Sabuncuoglu Tezcan and Philippe Soussan and Youssef Travaly and Zsolt Tokei and Eric Beyne and Bart Swinnen},
  journal={2011 IEEE International Interconnect Technology Conference},
Barrier reliability in 3D Through-Si Via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps… CONTINUE READING
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