Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]

@article{Pop2003ThermalAO,
  title={Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]},
  author={Eric Pop and R. W. Dutton and K H Goodson},
  journal={IEEE International Electron Devices Meeting 2003},
  year={2003},
  pages={36.6.1-36.6.4}
}
This paper explores the effect of confined dimensions and complicated geometries on the self-heating of ultra-thin body SOI and FinFET devices. A compact thermal model is introduced, incorporating the most advanced understanding of nanoscale heat conduction available. Novel device scaling is analyzed from a thermal point of view. We show device temperatures are very sensitive to the choice of drain and channel extension dimensions, and suggest a parameter design space which can help alleviate… CONTINUE READING
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Comparison of drain-ride temperature rise for SG-SO1 (solid lines) and FinFET (dashed lines) devices along ITRS roadmap. The FinFET channel width is 2 x fin height and the fin height is 4 x t

  • Kedzierski el al
  • IEEE TED vol
  • 2003
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