Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis

@article{Narasimhan1998TheoremPG,
  title={Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis},
  author={Naren Narasimhan and Elena Teica and Rajesh Radhakrishnan and Sriram Govindarajan and Ranga Vemuri},
  journal={Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)},
  year={1998},
  pages={392-399}
}
A formal specification and a proof of correctness of the widely-used force-directed list scheduling (FDLS) algorithm for resource-constrained scheduling in high-level synthesis systems is presented. The proof effort is conducted using a higher-order logic theorem prover. During the proof effort many interesting properties of the FDLS algorithm are discovered. These properties constitute a detailed set of formal assertions and invariants that should hold at various steps in the FDLS algorithm… CONTINUE READING

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