The soft error problem: an architectural perspective

@article{Mukherjee2005TheSE,
  title={The soft error problem: an architectural perspective},
  author={S. Mukherjee and J. Emer and S. Reinhardt},
  journal={11th International Symposium on High-Performance Computer Architecture},
  year={2005},
  pages={243-247}
}
  • S. Mukherjee, J. Emer, S. Reinhardt
  • Published 2005
  • Computer Science
  • 11th International Symposium on High-Performance Computer Architecture
  • Radiation-induced soft errors have emerged as a key challenge in computer system design. If the industry is to continue to provide customers with the level of reliability they expect, microprocessor architects must address this challenge directly. This effort has two parts. First, architects must understand the impact of soft errors on their designs. Second, they must select judiciously from among available techniques to reduce this impact in order to meet their reliability targets with minimum… CONTINUE READING
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    References

    SHOWING 1-10 OF 25 REFERENCES
    Techniques to reduce the soft error rate of a high-performance microprocessor
    • 279
    • PDF
    DIVA: a reliable substrate for deep submicron microarchitecture design
    • T. Austin
    • Computer Science
    • MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture
    • 1999
    • 802
    • PDF
    Modeling the effect of technology trends on the soft error rate of combinational logic
    • 1,513
    • PDF
    Characterizing the effects of transient faults on a high-performance processor pipeline
    • 412
    • PDF
    Timing vulnerability factors of sequentials
    • N. Seifert, N. Tam
    • Engineering
    • IEEE Transactions on Device and Materials Reliability
    • 2004
    • 130
    • PDF
    Cache scrubbing in microprocessors: myth or necessity?
    • 144
    • PDF
    IBM's S/390 G5 microprocessor design
    • 349