The multi-threaded, parity-protected 128-word register files on a dual-core Itanium/sup /spl reg//-family processor

@article{Fetzer2005TheMP,
  title={The multi-threaded, parity-protected 128-word register files on a dual-core Itanium/sup /spl reg//-family processor},
  author={Eric J. Fetzer and Lei Wang and Jasmine Jones},
  journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.},
  year={2005},
  pages={382-605 Vol. 1}
}
The dual-thread 18-port 128w/spl times/82b FPU register file, and the 22-port 128w/spl times/65b integer register file of the microprocessor is described. Parity embedded into each register provides soft error detection. The design integrates a charge-compensated thread switch and power-saving features to operate at 1.1V consuming 400mW at maximum frequency. 

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A Fully Bypassed Six-Issue Integer Datapath and Register File on the Itanium-2 Microprocessor,

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  • IEEE J. Solid-State Circuits,
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