The implementation of a 2-core multi-threaded Itanium/spl reg/-family processor

@article{Naffziger2005TheIO,
  title={The implementation of a 2-core multi-threaded Itanium/spl reg/-family processor},
  author={Samuel Naffziger and Brian Stackhouse and Tom Grutkowski},
  journal={2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.},
  year={2005},
  pages={43-48}
}
The next generation in the Itanium/spl reg/ processor family, code named Montecito, is introduced. Implemented in a 90nm 7M process, the processor has two dual-threaded cores integrated with 26.5MB of cache. Of the total of 1.72B transistors, 64M are dedicated to logic and the rest to cache. With both cores operating at full speed, the chip consumes 100W. 

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S. Naffziger
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