The impact of through silicon via proximity on CMOS device

@article{Jao2012TheIO,
  title={The impact of through silicon via proximity on CMOS device},
  author={Hsiu Jao and Y. Y. Lin and Will Liao and Billy Wu and Brady Huang and Lawrence Huang and Joe Huang and Steven Shih and J. P. Lin and P. S. Huang and M. Y. Tsai and C. Y. D. Huang},
  journal={2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)},
  year={2012},
  pages={43-45}
}
As device scaling becomes increasingly difficult, 3D integration with through silicon via (TSV) has emerged as a viable solution for addressing the requisite bandwidth and power efficiency challenges. However, mechanical stresses induced by the TSVs must be controlled in the 3D flow in order to preserve the electrical integrity of front-end devices. Since copper filling material of the TSV could causes stresses on silicon near the TSV, the impact of TSV proximity on CMOS must be evaluated at… CONTINUE READING
2 Citations
7 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-2 of 2 extracted citations

References

Publications referenced by this paper.
Showing 1-7 of 7 references

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

  • A. Mercha
  • VLSI technology ,
  • 2010
1 Excerpt

Impact of thinning and through silicon via proximity on HKMG first CMOS performance, VLSI technology

  • A. Mercha
  • IEEE Catalog Number: CFP1259B-ART
  • 2010
1 Excerpt

Design and fabrication of 3 D micr pro cessors ”

  • A. Mercha
  • MRSS Proceedings
  • 2007

Similar Papers

Loading similar papers…