The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity


We propose an algorithm for reducing the hardware complexity of linear phase FIR digital filters without resorting to an increase in the number of adder steps in the multiplier block adders. We aggressively reduce both the coefficient wordlength and the number of non-zero bits in the filter coefficients so that the adder step can be minimized. The hardware… (More)
DOI: 10.1109/ISCAS.2006.1692658

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