The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout

@article{Chow1999TheDO,
  title={The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout},
  author={P. Chow and Soon Ong Seo and J. Rose and K. Chung and G. Paez-Monzon and I. Rahardja},
  journal={IEEE Trans. Very Large Scale Integr. Syst.},
  year={1999},
  volume={7},
  pages={321-330}
}
  • P. Chow, Soon Ong Seo, +3 authors I. Rahardja
  • Published 1999
  • Computer Science
  • IEEE Trans. Very Large Scale Integr. Syst.
  • For Pt.I see ibid., vol.7, pp.191-7 (1999). Field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level… CONTINUE READING
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