The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout

@article{Chow1999TheDO,
  title={The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout},
  author={Paul Chow and Soon Ong Seo and Jonathan Rose and Kevin Chung and G. Paez-Monzon and I. Rahardja},
  journal={IEEE Trans. Very Large Scale Integr. Syst.},
  year={1999},
  volume={7},
  pages={321-330}
}
For Pt.I see ibid., vol.7, pp.191-7 (1999). Field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level… 

The Design of an SRAM-Based Field-Programmable Gate Array — Part I : Architecture

TLDR
The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custombuilt computer-aided design tools, and is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution.

The design of an SRAM-based field-programmable gate array. I. Architecture

TLDR
The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custom-built computer-aided design tools, and is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution.

Exploring static and dynamic flash-based FPGA design topologies

  • M. AbusultanS. Khatri
  • Computer Science, Engineering
    2016 IEEE 34th International Conference on Computer Design (ICCD)
  • 2016
TLDR
This work differs from previously proposed flash-based FPGAs, since it embeds the flash transistors directly within the logic and interconnect fabrics, and presents the tradeoff of delay, power dissipation and energy consumption of the various designs.

State-holding in Look-Up Tables: application to asynchronous logic

TLDR
The paper presents a new look-up table (LUT) architecture well-adapted to the Muller gate implementation that allows the combination of a single memory-point with combinational logic and is evaluated in CMOS, pass-transistor logic and 3-state logic.

Recent Trends in FPGA Architecture for Testing the Data path Using BSCAN

TLDR
A new architecture is proposed based on design of FPGA that has a hierarchical interconnection structural design through which a chip with an array of 16*16 LC is considered so that the interconnection of the proposed design is tested, and certain circuit sample from the design of a practical digital system is thus implemented.

A comparison of FinFET based FPGA LUT designs

TLDR
An evaluation of several FPGA LUT designs and demonstrates that all the FinFET based LUTs exhibit better delays and energy than the bulk based Lut.

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

TLDR
An experiment based on the implantation of the BIST architecture in a Virtex FPGA from Xilinx is developed, to show the feasibility of the proposed BIST scheme and its ability to detect the “smallest” delay faults in the LUTs.

Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design

  • Ian KuonJonathan Rose
  • Computer Science
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2011
TLDR
The range of area and delay tradeoffs possible by varying only the transistor sizing of a single architecture is larger than the ranges observed in past architectural experiments, and it is found that LUT size is one of the most useful parameters for trading off area anddelay.

A Study on Switch Block Patterns for Tileable FPGA Routing Architectures

TLDR
Results showed that in the context of tileable FPGA, a mix of Universal and Wilton switch block patterns lead to the best tradeoff in area, delay and routability, while Wiltonswitch block was the best choice in non-tileable FGPAs.

Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays

TLDR
The novel idea of a Multi-technology Field Programmable Gate Array (MT-FPGA) was proposed to extend the flexibility, rapid prototyping and reusability benefits associated with conventional FPGA technology into photonic and other multi-technology domain and give rise to the development of a wider class of programmable integrated systems.
...

References

SHOWING 1-10 OF 10 REFERENCES

The Design of an SRAM-Based Field-Programmable Gate Array — Part I : Architecture

TLDR
The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custombuilt computer-aided design tools, and is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution.

The design of an SRAM-based field-programmable gate array. I. Architecture

TLDR
The logic block and routing architecture of the FPGA was determined through experimentation with benchmark circuits and custom-built computer-aided design tools, and is an asymmetric tree of four-input lookup tables that are hard-wired together and a segmented routing architecture with a carefully chosen segment length distribution.

TRIPTYCH: A New FPGA Architecture

TLDR
Triptych is described, a new FPGA architecture that addresses two problems of current reprogrammable FPGAs: the large delays incurred in composing large functions and the strict division between routing and logic resources.

Logical effort: designing for speed on the back of an envelope

Outline t Introduction t Delay in a Logic Gate t Multi-stage Logic Networks t Choosing the Best Number of Stages t Example t Summary

Introduction to VLSI systems

His main interests are in Field-Programmable Gate Array (FPGA) architectures and CAD algorithms for FPGAs

  • His main interests are in Field-Programmable Gate Array (FPGA) architectures and CAD algorithms for FPGAs

Paul Chow (S'79{M'83) received the B.A.Sc. degree with honours in Engineering Science, and the M

  • 7] \Crosspoint solutions, performance benchmarks, rev 1.01
  • 1977

83) received the B.A.Sc. degree with honors in engineering science, and the M.A.Sc. and Ph.D. degrees in electrical engineering from the University of Toronto

  • 83) received the B.A.Sc. degree with honors in engineering science, and the M.A.Sc. and Ph.D. degrees in electrical engineering from the University of Toronto
  • 1977

White Oaks Road

  • White Oaks Road
  • 1300