The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout
@article{Chow1999TheDO, title={The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout}, author={P. Chow and Soon Ong Seo and J. Rose and K. Chung and G. Paez-Monzon and I. Rahardja}, journal={IEEE Trans. Very Large Scale Integr. Syst.}, year={1999}, volume={7}, pages={321-330} }
For Pt.I see ibid., vol.7, pp.191-7 (1999). Field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level… CONTINUE READING
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References
SHOWING 1-10 OF 13 REFERENCES
The design of an SRAM-based field-programmable gate array. I. Architecture
- Computer Science
- IEEE Trans. Very Large Scale Integr. Syst.
- 1999
- 97
ard P aez-Monz on, and Immanuel Rahardja, \The design of an SRAM-based eld-programmable gate array, Part I: Archi- tecture,
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
- 1999
A 1.2 m CMOS FPGA using cascaded logic blocks and segmented rout- ing,
- Abingdon EE&CS Books,
- 1991
Gerard PP aez-Monzz on, and Immanuel Rahardja, \The design of an SRAM-based eld-programmable gate array, Part I: Architecture
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems XX, no. YY
- 1999
83) received the B.A.Sc. degree with honors in engineering science, and the M.A.Sc. and Ph.D. degrees in electrical engineering from the University of Toronto
- 83) received the B.A.Sc. degree with honors in engineering science, and the M.A.Sc. and Ph.D. degrees in electrical engineering from the University of Toronto
- 1977