The clock distribution of the Power4 microprocessor

@article{Restle2002TheCD,
  title={The clock distribution of the Power4 microprocessor},
  author={P. Restle and C. Carter and J. P. Eckhardt and B. Krauter and B. D. McCredie and K. A. Jenkins and A. J. Weger and A. Mule},
  journal={2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)},
  year={2002},
  volume={1},
  pages={144-145 vol.1}
}
The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry. 
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