The circuit and physical design of the POWER4 microprocessor

@article{Warnock2002TheCA,
  title={The circuit and physical design of the POWER4 microprocessor},
  author={J. Warnock and J. M. Keaty and John G. Petrovick and J. G. Clabes and C. J. Kircher and B. L. Krauter and P. J. Restle and B. A. Zoric and C. J. Anderson},
  journal={IBM J. Res. Dev.},
  year={2002},
  volume={46},
  pages={27-52}
}
  • J. Warnock, J. M. Keaty, +6 authors C. J. Anderson
  • Published in IBM J. Res. Dev. 2002
  • Computer Science
  • The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the… CONTINUE READING

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