The case for the reduced instruction set computer

@article{Patterson1980TheCF,
  title={The case for the reduced instruction set computer},
  author={David A. Patterson and David R. Ditzel},
  journal={SIGARCH Comput. Archit. News},
  year={1980},
  volume={8},
  pages={25-33}
}
One of the primary goals of computer architects is to design computers that are more costeffective than their predecessors. [...] Key Result This paper will argue that the next generation of VLSI computers may be more effectively implemented as RISC's than CISC's.Expand
RISC I: a reduced instruction set VLSI computer
TLDR
The architecture of RISC I and its novel hardware support scheme for procedure call/return are presented and it appears possible to build a single chip computer faster than VAX 11/780 and to have a much shorter design time. Expand
A VLSI RISC
TLDR
The hypothesis is that by reducing the instruction set one can design a suitable VLSI architecture that uses scarce resources more effectively than a CISC, and expects this approach to reduce design time, design errors, and the execution time of individual instructions. Expand
A RISCy approach to VLSI
TLDR
The Reduced Instruction Set Computer (RISC) Project investigates a VLSI alternative to this trend by designing a reasonable compromise between high performance for high-level language programs and a simple single-chip implementation. Expand
The advantages of RISC architectures
TLDR
A complete RISC system has been designed to partition efficiently onto four custom chips, which combines with standard memory devices to deliver superminicomputer processing performance, with full support for multi-tasking and virtual memory, at a similar silicon cost to standard PC. Expand
Preliminary analysis of RISC architectures performance
TLDR
Preliminary results indicate that there is a strong chance that RISC-type computers could be designed to function as efficient low-cost systems. Expand
Comments on "the case for the reduced instruction set computer," by Patterson and Ditzel
TLDR
A careful comparison between a RISC and a CISC would seem to require a complete design of the hardware and microcode for both, construction or simulation of the processors, the writing of compilers and possibly an operating system, and performance measurement across a variety of applications. Expand
The commercialization of RISC: Strategies for the creation of dominant designs
TLDR
This paper discusses the development and commercialization of RISC architectures, focusing on the licensing strategies of Sun and MIPS Computer Systems, two pioneers in RISC microprocessors. Expand
Reduced instruction set computer (RISC)
TLDR
Until 1975, computer architecture and, consequently, computer design and implementation had grown more complicated with each successive generation because the nature of the compiler changed or because the compiler didn't change when it should have. Expand
How useful are complex instructions?: a case study using the MG8000
TLDR
It is concluded that a small number of carefully selected complex instructions can usefully increase the performance of both CISC and RISC processors. Expand
Re-evaluation of the RISC I
TLDR
This paper hopes to more completely evaluate the reduced Instruction Set Computer, a relatively new concept in c(mput-er architecture, by removing extraneous factors and re-evaluating the RISC I. Expand
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 15 REFERENCES
A 32-bit processor design
TLDR
This paper describes a user-level instruction set for a 32-bit processor which seems exceptionally attractive to at least one software person (the author). Expand
Design Considerations for Single-Chip Computers of the Future
TLDR
It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. Expand
Static and Dynamic Characteristics of XPL Programs
TLDR
The main interest is in the discovery of primitive operations, implied by the semantics of a programming language, that can be added to the firmware or hardware of a computer to improve overall system performance. Expand
An instruction timing model of CPU performance
A model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBMExpand
Microprogramming: principles and practices
details how one can use a four-state cell to store logic which has been ex'and-not' and 'exclusive-or' functions as well as the standard sum of products ity to recognize these additional functionsExpand
Measures of Op-Code Utilization
TLDR
Two measures of the effective use of machine instructions are discussed and applied to samples of hand-coded programs and object code. Expand
Retrospective on high-level language computer architecture
TLDR
The intent of this paper is to identify and discuss several issues applicable to high-level language computer architecture, to provide a more concrete definition of high- level language computers, and to suggest a direction for high-levels language computer architectures of the future. Expand
A 32-bit Processor Design," Computer Science Technical Report
  • 1979
Cragon, in his talk presenting the paper "The Case Against High-Level Language Computers
  • at the International Workshop on High-Level Language Computer Architecture
  • 1980
in his talk presenting the paper "The Case Against High-Level Language Computers," at the International Workshop on High-Level Language
  • Computer Architecture,
  • 1980
...
1
2
...