The case for the reduced instruction set computer

@article{Patterson1980TheCF,
  title={The case for the reduced instruction set computer},
  author={David A. Patterson and David R. Ditzel},
  journal={SIGARCH Comput. Archit. News},
  year={1980},
  volume={8},
  pages={25-33}
}
One of the primary goals of computer architects is to design computers that are more costeffective than their predecessors. [...] Key Result This paper will argue that the next generation of VLSI computers may be more effectively implemented as RISC's than CISC's.Expand
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218 Citations
Highly Influential Citations
7
Background Citations
50
Methods Citations
13

218 Citations

Citation Type

Citation Type

RISC I: a reduced instruction set VLSI computer
TLDR
The architecture of RISC I and its novel hardware support scheme for procedure call/return are presented and it appears possible to build a single chip computer faster than VAX 11/780 and to have a much shorter design time. Expand
A VLSI RISC
TLDR
The hypothesis is that by reducing the instruction set one can design a suitable VLSI architecture that uses scarce resources more effectively than a CISC, and expects this approach to reduce design time, design errors, and the execution time of individual instructions. Expand
A RISCy approach to VLSI
TLDR
The Reduced Instruction Set Computer (RISC) Project investigates a VLSI alternative to this trend by designing a reasonable compromise between high performance for high-level language programs and a simple single-chip implementation. Expand
The advantages of RISC architectures
TLDR
A complete RISC system has been designed to partition efficiently onto four custom chips, which combines with standard memory devices to deliver superminicomputer processing performance, with full support for multi-tasking and virtual memory, at a similar silicon cost to standard PC. Expand
Preliminary analysis of RISC architectures performance
TLDR
Preliminary results indicate that there is a strong chance that RISC-type computers could be designed to function as efficient low-cost systems. Expand
Comments on "the case for the reduced instruction set computer," by Patterson and Ditzel
TLDR
A careful comparison between a RISC and a CISC would seem to require a complete design of the hardware and microcode for both, construction or simulation of the processors, the writing of compilers and possibly an operating system, and performance measurement across a variety of applications. Expand
The commercialization of RISC: Strategies for the creation of dominant designs
TLDR
This paper discusses the development and commercialization of RISC architectures, focusing on the licensing strategies of Sun and MIPS Computer Systems, two pioneers in RISC microprocessors. Expand
Reduced instruction set computer (RISC)
TLDR
Until 1975, computer architecture and, consequently, computer design and implementation had grown more complicated with each successive generation because the nature of the compiler changed or because the compiler didn't change when it should have. Expand
How useful are complex instructions?: a case study using the MG8000
TLDR
It is concluded that a small number of carefully selected complex instructions can usefully increase the performance of both CISC and RISC processors. Expand
Re-evaluation of the RISC I
TLDR
This paper hopes to more completely evaluate the reduced Instruction Set Computer, a relatively new concept in c(mput-er architecture, by removing extraneous factors and re-evaluating the RISC I. Expand
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