The case for registered routing switches in field programmable gate arrays

@inproceedings{Singh2001TheCF,
  title={The case for registered routing switches in field programmable gate arrays},
  author={D. Singh and S. Brown},
  booktitle={FPGA '01},
  year={2001}
}
FPGAs are characterized by a programmable interconnect that contains highly resistive and capacitive elements. While the configurable structure of the interconnect allows for the implementation of arbitrary circuits, it has also become a significant bottleneck for high-speed circuits. Even if there are only a few signal paths that run along long stretches of interconnect, it is these paths that may determine the maximum operating frequency of the circuit. In this paper we investigate… Expand
43 Citations
Constrained clock shifting for field programmable gate arrays
  • 29
  • PDF
Techniques for timing closure on high-speed field programmable gate arrays
  • 2
  • PDF
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor
  • 1
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
  • Allan Carroll, C. Ebeling
  • Computer Science
  • 2006 International Conference on Field Programmable Logic and Applications
  • 2006
  • 5
The sfra: a fixed frequency fpga architecture
  • 5
  • PDF
A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps
  • Ting-Jung Lin, Wei Zhang, N. Jha
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2014
  • 18
Supporting high-performance pipelined computation in commodity-style fpgas
  • 2
  • Highly Influenced
  • PDF
PITIA: an FPGA for throughput-intensive applications
  • 3
...
1
2
3
4
5
...

References

Optimizing synchronous circuitry
  • Journal of VLSI and Computer Systems, pages 41{67
  • 1983