The cache and memory subsystems of the IBM POWER8 processor


subsystems of the IBM POWER8 processor W. J. Starke J. Stuecheli D. M. Daly J. S. Dodson F. Auernhammer P. M. Sagmeister G. L. Guthrie C. F. Marino M. Siegel B. Blaner In this paper, we describe the IBM POWER8i cache, interconnect, memory, and input/output subsystems, collectively referred to as the Bnest.[ This paper focuses on the enhancements made to the… (More)
DOI: 10.1147/JRD.2014.2376131


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