The XMOS Architecture and XS1 Chips

@article{May2012TheXA,
  title={The XMOS Architecture and XS1 Chips},
  author={David May},
  journal={IEEE Micro},
  year={2012},
  volume={32},
  pages={28-37}
}
The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications, and I/O are supported by the instruction set of the XCORE processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed. 

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