The VTR project: architecture and CAD for FPGAs from verilog to routing

  title={The VTR project: architecture and CAD for FPGAs from verilog to routing},
  author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeffrey B. Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Helge Anderson},
To facilitate the development of future FPGA architectures and CAD tools -- both embedded programmable fabrics and pure-play FPGAs -- there is a need for a large scale, publicly available software suite that can synthesize circuits into easily-described hypothetical FPGA architectures. These circuits should be captured at the HDL level, or higher, and pass through logical and physical synthesis. Such a tool must provide detailed modelling of area, performance and energy to enable architecture… CONTINUE READING
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