The Twin-Transistor Noise-Tolerant Dynamic Circuit Technique

@inproceedings{Balamurugan2001TheTN,
  title={The Twin-Transistor Noise-Tolerant Dynamic Circuit Technique},
  author={Ganesh Balamurugan and N. R. Shanbhag},
  year={2001}
}
This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35m CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1 8 (for an AND gate) and2 5 (for an adder carry chain) over domino at the same speed. A multiply–accumulate circuit has… CONTINUE READING
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