The Tiny Tera: A Packet Switch Core

Abstract

In this paper, we present the Tiny Tera: a small packet switch with an aggregate bandwidth of 320Gb/s. The Tiny Tera is a CMOS-based input-queued, fixed-size packet switch suitable for a wide range of applications such as a highperformance ATM switch, the core of an Internet router or as a fast multiprocessor interconnect. Using off-the-shelf technology, we plan to demonstrate that a very highbandwidth switch can be built without the need for esoteric optical switching technology. By employing novel scheduling algorithms for both unicast and multicast traffic, the switch will have a maximum throughput close to 100%. Using novel highspeed chip-to-chip serial link technology, we plan to reduce the physical size and complexity of the switch, as well as the system pin-count.

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@article{McKeown1997TheTT, title={The Tiny Tera: A Packet Switch Core}, author={Nick McKeown and Martin Izzard and Adisak Mekkittikul and William Ellersick and Mark Horowitz}, journal={CoRR}, year={1997}, volume={cs.NI/9810006} }