The Promise of High-Performance Reconfigurable Computing

@article{ElGhazawi2008ThePO,
  title={The Promise of High-Performance Reconfigurable Computing},
  author={Tarek A. El-Ghazawi and Esam El-Araby and Miaoqing Huang and Kris Gaj and V. Kindratenko and Duncan A. Buell},
  journal={Computer},
  year={2008},
  volume={41}
}
Several high-performance computers now use field-programmable gate arrays as reconfigurable coprocessors. The authors describe the two major contemporary HPRC architectures and explore the pros and cons of each using representative applications from remote sensing, molecular dynamics, bioinformatics, and cryptanalysis. 

Figures and Tables from this paper

Nallatech In-Socket FPGA Front-Side Bus Accelerator
Field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.
Sorting on architecturally diverse computer systems
TLDR
This work investigates a family of approaches that exploit characteristics fairly unique to reconfigurable hardware that maximize the benefit associated with high-bandwidth, multiple-port access to memory.
Optimization of Shared High-Performance Reconfigurable Computing Resources
TLDR
An overview of the analytical model and its application for optimization and scheduling of high-performance reconfigurable computing (HPRC) resources are provided and cost functions for minimum runtime and other optimization problems commonly found in shared computing resources are examined.
High Performance Computing with FPGAs
TLDR
The results in the paper and in the literature show that, with the proper programming tool set, FPGAs can speedup computation kernels significantly with respect to traditional processors.
Integration of a multi-FPGA system in a common cluster environment
  • Oliver Knodel, R. Spallek
  • Computer Science
    2013 23rd International Conference on Field programmable Logic and Applications
  • 2013
TLDR
This work introduces a simple and scalable integration of the FPGAs in a common cluster architecture to permit an easy access to these resources and allow an efficient use of distributed FPGA resources.
Low cost high performance reconfigurable computing
TLDR
The proof of the concept of the SMILE HPRC has been exhaustively tested with two complex and demanding applications: the Monte Carlo financial simulation and the Boolean Synthesis using Genetic Algorithms.
The Role of Programming Models on Reconfigurable Computing Fabrics
TLDR
FPGAs are common-place for early prototyping, and more recently even for deployment, given such characteristics as the substantial increase of resources in the high-end FPGAs, the ability to “zero-cost” update of hardware in early timing windows where modifications might have abstraCt.
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
TLDR
This article presents an application-specific design methodology for multiprocessor-on-programmable-chip architectures that target applications involving large matrices and floating-point operations and aims to customize the architecture to match the diverse computation and communication requirements of the application tasks.
High-Performance Reconfigurable Computing Granularity
TLDR
This article provides a description of fine and coarse-grained reconfigurable hardware for high performance computing and is mainly concerned with the granularity aspect in high performance reconfigured computing.
High-Performance Reconfigurable Computing
TLDR
To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption.
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 14 REFERENCES
An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers
TLDR
This paper demonstrates an efficient implementation of IDEA encryption, using two of the leading reconfigurable computers available, SRC Computers’ SRC-6E and Star Bridge Systems’ HC-36, and compares the hardware architecture and programming model of these reconfigurability computers, and the implementation of a commonIDEA encryption architecture in both platforms.
Implementation trade-offs of Triple DES in the SRC-6 e Reconfigurable Computing Environment
TLDR
The architecture and programming model of the SRC-6E Reconfigurable Computing Environment is overviewed, and the trade-offs associated with the different possible implementations are demonstrated, using Triple-DES cryptographic application.
A case study in porting a production scientific supercomputing application to a reconfigurable computer
  • V. Kindratenko, D. Pointer
  • Computer Science
    2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
  • 2006
TLDR
The rationale in choosing the development path taken and the general framework for porting an existing scientific code, such as NAMD, to the SRC-6 platform are presented and discussed in detail and the results are applicable to the large class of problems in scientific computing.
FPGAs vs. CPUs: trends in peak floating-point performance
TLDR
This paper examines the impact of Moore's Law on the peak floating-point performance of FPGAs and results show that peak FPGA floating- point performance is growing significantly faster than peak CPU performance for a CPU.
A Segmentation Model for Partial Run-Time Reconfiguration
  • M. Taher, T. El-Ghazawi
  • Computer Science
    2006 International Conference on Field Programmable Logic and Applications
  • 2006
TLDR
This work proposes a more general virtual-memory-like technique that discovers related functions and groups them into variable size blocks (segments) and can exploit both spatial and temporal processing locality simultaneously.
The RC5 Encryption Algorithm
This document describes the RC5 encryption algorithm, a fast symmetric block cipher suitable for hardware or software implementations. A novel feature of RC5 is the heavy use of data-dependent
Scalable molecular dynamics with NAMD
NAMD is a parallel molecular dynamics code designed for high‐performance simulation of large biomolecular systems. NAMD scales to hundreds of processors on high‐end parallel platforms, as well as
Bioinformatics: Sequence and Genome Analysis
TLDR
The aim of this book is to provide a grounding in probability and statistical analysis of sequence alignments, as well as a jumping-off point for future research into bioinformatics programming.
Automatic reduction of hyperspectral imagery using wavelet spectral analysis
TLDR
It is shown that automatic wavelet reduction yields better or comparable classification accuracy for hyperspectral data, while achieving substantial computational savings.
Experience with Early Reconfigurable High- Performance Computers
  • Experience with Early Reconfigurable High- Performance Computers
  • 2006
...
1
2
...