The K computer: Japanese next-generation supercomputer development project

@article{Yokokawa2011TheKC,
  title={The K computer: Japanese next-generation supercomputer development project},
  author={Mitsuo Yokokawa and Fumiyoshi Shoji and Atsuya Uno and Motoyoshi Kurokawa and Tadashi Watanabe},
  journal={IEEE/ACM International Symposium on Low Power Electronics and Design},
  year={2011},
  pages={371-372}
}
The K computer is a distributed memory supercomputer system consisting of more than 80,000 compute nodes which is being developed by RIKEN as a Japanese national project. Its performance is aimed at achieving 10 peta-flops sustained in the LINPACK benchmark. The system is under installation and adjustment. The whole system will be operational in 2012. 

Figures from this paper

K computer: 8.162 PetaFLOPS massively parallel scalar supercomputer built with over 548k cores

Many high-performance CPUs employ a multicore architecture with a moderate clock frequency and wide instruction issue, including SIMD extensions, to achieve high performance while retaining a

Overview of the K computer System

The K computer system is described and the measures taken for reducing power consumption and achieving high reliability and high availability are presented and the results of implementing those measures are presented.

High Performance Computing through Parallel and Distributed Processing

The Programming concepts like threads, fork and sockets are discussed with some simple examples for HPC and Parallel and Distributed algorithms are discussed based on Parallel and distributed Processors to achieve HPC.

Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE

Evaluation results clearly indicate that the high sustained memory performance per core enables the modern vector supercomputer to achieve outstanding performances that are unreachable by simply increasing the number of fine-grain scalar processor cores.

K MapReduce: A scalable tool for data-processing and search/ensemble applications on large-scale supercomputers

The results of experimental performance studies of KMR are presented and it is shown how KMR can be used to program real-world scientific applications such as meta-genome search and replica-exchange molecular dynamics.

Implementation and evaluation of the HPC challenge benchmark in the XcalableMP PGAS language

The goal of the present paper is to clarify XcalableMP’s productivity and performance and implement and evaluate the high performance computing challenge benchmark, namely, EP STREAM Triad, High Performance Linpack, Global fast Fourier transform, and RandomAccess on the K computer using up to 16,384 compute nodes and a generic cluster system.

Highly scalable eigensolvers for petaflop applications

Efficiency and scalability of the new eigensolver are unprecedented and result in an up to 10-fold improvement compared to current state-of-the-art libraries.

Updating the Energy Model for Future Exascale Systems

This paper introduces a major update to the “heavyweight” (modern server-class multi-core chips) model, with a detailed discussion on the underlying projections as to technology, chip layout and microarchitecture, and system characteristics.
...

References

SHOWING 1-7 OF 7 REFERENCES

Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing

The Sparc64 VIIIfx eight-core processor, developed for use in petascale computing systems, runs at speeds of up to 2 GHz and achieves a peak performance of 128 gigaflops while consuming as little as

Tofu: A 6D Mesh/Torus Interconnect for Exascale Computers

A new architecture with a six-dimensional mesh/torus topology achieves highly scalable and fault-tolerant interconnection networks for large-scale supercomputers that can exceed 10 petaflops.

The SPARC architecture manual : version 9

This document describes the development of the SPARC-V9 Architecture and some of the technologies used in its development, as well as some of its components, including the memory models, which were designed for this architecture.

SPARC64™ VIIIfx: Fujitsu’s New Generation Octo Core Processor for PETA Scale computing

Sparc Joint Programming Specification (JPS1): Commonality, architecture manual. Sun Microsystems and Fujitsu Ltd

  • Sparc Joint Programming Specification (JPS1): Commonality, architecture manual. Sun Microsystems and Fujitsu Ltd
  • 2002

ICC: An interconnect controller for the Tofu interconnect architecture Hot Chips22

  • ICC: An interconnect controller for the Tofu interconnect architecture Hot Chips22
  • 2010

ICC: An interconnect controller for the Tofu interconnect architecture,

  • Hot Chips22,
  • 2010