The Impact of NBTI on the Performance of Combinational and Sequential Circuits

@article{Wang2007TheIO,
  title={The Impact of NBTI on the Performance of Combinational and Sequential Circuits},
  author={Wenping Wang and Shengqi Yang and Sarvesh Bhardwaj and Rakesh Vattikonda and Sarma B. K. Vrudhula and Frank Liu and Yu Cao},
  journal={2007 44th ACM/IEEE Design Automation Conference},
  year={2007},
  pages={364-369}
}
Negative-bias-temperature-instability (NBTI) has become the primary limiting factor of circuit lifetime. In this work, we develop a general framework for analyzing the impact of NBTI on the performance of a circuit, based on various circuit parameters such as the supply voltage, temperature, and node switching activity of the signals etc. We propose an efficient method to predict the degradation of circuit performance based on circuit topology and the switching activity of the signals over long… 

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay

TLDR
Experimental results demonstrate that the delay increase of timing-critical paths can be mitigated significantly under long time NBTI effect (10-year) by only applying a small number of vectors.

An efficient method to identify critical gates under circuit aging

TLDR
It is demonstrated in this work that it is feasible to reliably predict the relative importance of gates under NBTI and that in average only 1% of total gates need to be protected in order to control the timing degradation within 10% in ten years.

Design Techniques for NBTI-Tolerant Power-Gating Architectures

TLDR
This brief proposes a set of efficient NBTI-aware circuit design solutions that aim at improving the lifetime stability of power-gated circuits by means of oversizing, body biasing, and stress-probability reduction while minimizing the design overheads.

NBTI Degradation: A Problem or a Scare?

TLDR
The proposed logic level simulation methodology is validated by showing that it is accurate within 1% of the reference model, and the overall delay degradation of large digital circuits due to NBTI is relatively small.

On the simulation of NBTI-Induced performance degradation considering arbitrary temperature and voltage variations

  • Ting WangQ. Xu
  • Engineering
    2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)
  • 2014
TLDR
This work proposes a comprehensive NBTI analytical model that explicitly takes supply voltage, duty cycle and temperature variations into consideration and presents an efficient simulation framework for system lifetime prediction by running representative workloads only.

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques

TLDR
This paper proposes two gate replacement algorithms, DGR and DCBGR, together with optimal input vector selection, to simultaneously reduce the leakage power and mitigate NBTI-induced degradation.

NBTI-Aware Nanoscaled Circuit Delay Assessment and Mitigation

As semiconductor manufacturing entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this

Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect

TLDR
Experimental results show that by protecting the critical nodes found by the node criticality computation algorithm under the NBTI aware timing analysis and optimization framework, circuit delay degradation can be reduced by up to 50%.

On predicting NBTI-induced circuit aging by isolating leakage change

TLDR
This paper proposes to use the isolated leakage change in critical path from full-chip leakage measurement result to predict NBTI-induced circuit aging and predicts delay degradation on arbitrary critical path based on the correlation between leakage change and delay increase.
...

References

SHOWING 1-10 OF 14 REFERENCES

An Analytical Model for Negative Bias Temperature Instability

Negative bias temperature instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, the effect of NBTI has

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits

TLDR
A sizing algorithm is proposed taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time and showing that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years.

Modeling and minimization of PMOS NBTI effect for robust nanometer design

TLDR
A predictive model is developed for the degradation of NBTI in both static and dynamic operations and key insights are obtained for the development of robust design solutions.

Impact of NBTI on the temporal performance degradation of digital circuits

Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the

Dynamic NBTI of PMOS transistors and its impact on device lifetime

  • G. ChenK. Y. Chuah D. Kwong
  • Engineering
    2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.
  • 2003
We report a new NBTI phenomenon for p-MOSFETs with ultra thin gate oxides. We demonstrate that in a CMOS inverter circuit, the interface traps generated under NBTI stressing in a p-MOSFET

NBTI reliability analysis for a 90 nm CMOS technology

  • H. PuchnerL. Hinh
  • Engineering
    Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)
  • 2004
We present a comprehensive empirical study to investigate the impact of negative bias temperature instability (NBTI) on device performance and reliability. The NBTI lifetime is calculated for

A comprehensive model of PMOS NBTI degradation

Predictive Modeling of the NBTI Effect for Reliable Design

This paper presents a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation. Based on the reaction-diffusion (R-D) mechanism,

Material dependence of hydrogen diffusion: implications for NBTI degradation

Negative bias temperature instability (NBTI) is known to exhibit significant recovery upon removal of the gate voltage. The process dependence of this recovery behavior is studied by using the time

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

This paper presents a new reliability scaling scenario for CMOS devices with direct-tunneling ultra-thin gate oxide. Device degradation due to bias-temperature instability (BTI) was studied. First,