The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

  title={The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis},
  author={Wenping Wang and Shengqi Yang and S. Bhardwaj and S. Vrudhula and Frank Liu and Yu Cao},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  • Wenping Wang, Shengqi Yang, +3 authors Yu Cao
  • Published 2010
  • Computer Science, Engineering
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The… Expand
Modeling and simulation for NBTI-considered path delay prediction in logical circuit
NBTI (Negative Bias Temperature Instability) is a major concern in long-time circuit performance. In this paper, NBTI degradation models of basic logic gates have been developed based on theExpand
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The negative-bias temperature instability (NBTI) is one of the dominant aging degradation mechanisms in today Very Large Scale Integration (VLSI) Integrated Circuits (IC). With the further decreasingExpand
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A hierarchical model to compute NBTI-induced logic path delays at gate level considering PV is proposed, derived based on intensive SPICE simulations of basic logic gates at transistor level under PV. Expand
Self-impact of NBTI effect on the degradation rate of threshold voltage in PMOS transistors
A simulation framework is developed to dynamically estimate the effect of NBTI on power consumption of the circuit and consequently the operating temperature and results show that estimated degradation in Vth is about 4.1% less than the predicted amount by current models. Expand
Compact Modeling of BTI for Circuit Reliability Analysis
The aging process due to Bias Temperature Instability (BTI) is a key limiting factor of circuit lifetime in contemporary CMOS design. Threshold voltage shift induced by BTI is a strong function ofExpand
Prediction of NBTI Degradation in Dynamic Voltage Frequency Scaling Operations
The closed-form reaction-diffusion and trapping/detrapping models are revises to improve their aging prediction, under the situation when supply voltage, frequency, and duty factor consecutively change and are able to provide convincing aging predictions. Expand
Failure Analysis of Asymmetric Aging Under NBTI
With CMOS technology scaling, design for reliability has become an important step in the design cycle and increased the need for efficient and accurate aging simulation methods during the designExpand
Impact of NBTI on digital integrated circuits in FinFET technologies
This work evaluates the performance of FinFET-based combinational circuits considering BTI stress and thermal effect of supply voltage and frequency variations and introduces a DVFS based power reduction approach that scales down the supply voltage of hot circuits to maintain the performance. Expand
Accurate NBTI-induced Gate Delay Modeling Based on Intensive SPICE Simulations
One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage ofExpand
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system
This paper uses a physical probability model of trap generation for both NBTI and GOBD and finds the stress conditions that make each of the two mechanisms dominant in the power/ground signal. Expand


An Analytical Model for Negative Bias Temperature Instability
Negative bias temperature instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, the effect of NBTI hasExpand
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A predictive model is developed for the degradation of NBTI in both static and dynamic operations and key insights are obtained for the development of robust design solutions. Expand
Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology
A unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects is presented, and it is demonstrated that the proposed method very well predicts the degradation. Expand
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits
A sizing algorithm is proposed taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time and showing that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years. Expand
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability concerns in sub-100 nm technologies. So far, studies of NBTI and its impact on circuit performance have assumedExpand
Impact of negative bias temperature instability on digital circuit reliability
  • V. Reddy, A. Krishnan, +4 authors S. Krishnan
  • Materials Science
  • 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320)
  • 2002
We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determinedExpand
Dynamic NBTI of PMOS transistors and its impact on device lifetime
  • G. Chen, K. Y. Chuah, +5 authors D. Kwong
  • Materials Science
  • 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.
  • 2003
We report a new NBTI phenomenon for p-MOSFETs with ultra thin gate oxides. We demonstrate that in a CMOS inverter circuit, the interface traps generated under NBTI stressing in a p-MOSFETExpand
Impact of NBTI on the temporal performance degradation of digital circuits
Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict theExpand
NBTI reliability analysis for a 90 nm CMOS technology
  • H. Puchner, L. Hinh
  • Materials Science
  • Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)
  • 2004
We present a comprehensive empirical study to investigate the impact of negative bias temperature instability (NBTI) on device performance and reliability. The NBTI lifetime is calculated forExpand
A comprehensive model of PMOS NBTI degradation
A comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model is constructed and it is demonstrated how to solve the reaction-diffusion equations in a way that emphasizes the physical aspects of the degradation process and allows easy generalization of the existing work. Expand