The Impact of BTI Variations on Timing in Digital Logic Circuits

  title={The Impact of BTI Variations on Timing in Digital Logic Circuits},
  author={Jianxin Fang and S. S. Sapatnekar},
  journal={IEEE Transactions on Device and Materials Reliability},
A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo… CONTINUE READING
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