The Impact of Aging Effects and Manufacturing Variation on SRAM Soft-Error Rate

@article{Cannon2008TheIO,
  title={The Impact of Aging Effects and Manufacturing Variation on SRAM Soft-Error Rate},
  author={Ethan H. Cannon and A. J. KleinOsowski and Rouwaida Kanj and D.D. Reinhardt and Rajiv V. Joshi},
  journal={IEEE Transactions on Device and Materials Reliability},
  year={2008},
  volume={8},
  pages={145-152}
}
This paper describes modeling and hardware results of how the soft-error rate (SER) of a 65-nm silicon-on-insulator SRAM memory cell changes over time, as semiconductor aging effects shift the SRAM cell behavior. This paper also describes how the SER changes in the presence of systematic and random manufacturing variation. 
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References

SHOWING 1-10 OF 17 REFERENCES
The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction
  • R. Baumann
  • Computer Science
  • Digest. International Electron Devices Meeting,
  • 2002
TLDR
Memory and logic scaling trends are discussed along with a method for determining logic SER, the soft error rate of advanced CMOS devices, which may limit future product reliability. Expand
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
Reductions in CMOS SRAM cell static noise margin (SNM) due to intrinsic threshold voltage fluctuations in uniformly doped minimum-geometry cell MOSFETs are investigated for the first time usingExpand
Impact of process variation on soft error vulnerability for nanometer VLSI circuits
In this paper, the impact of process variation on-soft error vulnerability for nanometer VLSI circuits is studied. Particle strike is modeled in SPICE as a current source connected to the node ofExpand
Sram Operational Voltage Shifts in the Presence of Gate Oxide Defects in 90 NM SOI
The continued scaling of gate oxide thickness in CMOS transistors has made dielectric integrity paramount to system functionality at low voltages. In this paper, the effect of gate oxide breakdown onExpand
Modeling the effect of technology trends on the soft error rate of combinational logic
TLDR
An end-to-end model is described and validated that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs and predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SERper chip of unprotected memory elements. Expand
SRAM SER in 90, 130 and 180 nm bulk and SOI technologies
We investigate the soft error rate (SER) of bulk and SOI SRAMs at the 90, 130 and 180 nm technology nodes. We use accelerated testing and Monte Carlo modeling to determine SER sensitivity toExpand
A Comparative Study on the Soft-Error Rate of Flip-Flops from 90-nm Production Libraries
This paper presents a study using alpha- and neutron-accelerated tests to characterize soft error rates (SER) of flip-flops that are used in 90-nm CMOS production designs. The investigated flip-flopsExpand
Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices
This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, oneExpand
Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells
Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particlesExpand
Critical charge calculations for a bipolar SRAM array
  • L. B. Freeman
  • Materials Science, Computer Science
  • IBM J. Res. Dev.
  • 1996
TLDR
It is concluded that a range in values of the critical charge of a cell due to normal manufacturing and operating tolerances must be considered when calculating soft-error rates for a chip. Expand
...
1
2
...