The Gmicro/500 superscalar microprocessor with branch buffers

@article{Uchiyama1993TheGS,
  title={The Gmicro/500 superscalar microprocessor with branch buffers},
  author={Kunio Uchiyama and Fumio Arakawa and Susumu Narita and Hirokazu Aoki and Ikuya Kawasaki and Shigezumi Matsui and Mitsuyoshi Yamamoto and Norio Nakagawa and Ikuo Kudo},
  journal={IEEE Micro},
  year={1993},
  volume={13},
  pages={12-22}
}
The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively… 
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