The Gmicro/500 superscalar microprocessor with branch buffers

  title={The Gmicro/500 superscalar microprocessor with branch buffers},
  author={Kunio Uchiyama and Fumio Arakawa and Susumu Narita and Hirokazu Aoki and Ikuya Kawasaki and Shigezumi Matsui and Mitsuyoshi Yamamoto and Norio Nakagawa and Ikuo Kudo},
  journal={IEEE Micro},
The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively… 
8 Citations

Figures from this paper

The Microarchitecture of Pipelined and Superscalar Computers

The Microarchitecture of Pipelined and Superscalar Computers has been specifically developed as a textbook for advanced undergraduate or graduate level instruction and makes an invaluable reference for microprocessor design engineers and those seeking to pursue research in the area.


  • Computer Science
  • 1999
An underlying deterministic framework can be identified for the fascinating evolution of microprocessors and it is shown that this immense performance increase could only be achieved by the subsequent introduction of temporal, issue and intrainstruction parallelism.

Control Flow: Branching and Control Hazards

This chapter shall discuss a number of measures for dealing with the branch latency, which is arguably the hardest problem in the design of high-performance instruction pipelines.

Superscalar instruction issue

  • D. Sima
  • Computer Science, Education
    IEEE Micro
  • 1997
The article demonstrates a concise way to represent the design space using DS trees, reviews the most frequently used issue schemes, and highlights trends for each design aspect of instruction issue.

Symbolic Debugging of Optimized Behavioral

  • Computer Science
  • 1999
A set of techniques that, given a behavioral speciication CDFG, enforce computation of a selected subset Vcut of user variables such that all other variables v 2 CDFG can be computed from Vcut and this enforcement has minimal impact on the optimization potential of the computation.

Symbolic debugging of globally optimized behavioral specifications

This work presents an approach for a symbolic debugger to retrieve and display the value of a variable correctly and efficiently in response to a user inquiry about the variable in the source specification, and describes how transformations affect the retrieval of source values.



The Gmicro/300 32-bit microprocessor

A high-end microprocessor, the Gmicro/300, based on the TRON architecture specification is described, which executes an instruction with a memory operand and a register operand in one clock cycle.

GMICRO/500 microprocessor: pipeline structure of superscalar architecture

The GMICRO/500 pipelined instruction execution mechanism is described. The 5-stage dual-pipeline superscalar architecture is examined and examples of basic instruction execution timing are analyzed,

The Gmicro/100 32-bit microprocessor

The prejump mechanism, implemented as a hardware solution for the jump problem, executes benchmark programs 16.8% faster on the average and Optimized microinstructions permit bitmap-manipulation instructions to perform two to five times faster than the software loops.

Realization of Gmicro/200

The Gmicro/200, a microprocessor that has been developed as part of Japan's TRON (The Real-Time Operating Nucleus) project, is described and features of the instruction set; memory management; handling of exceptions, interrupts and traps; and the implementation of the G micro/200 are discussed.

A CMOS 50 MHz CISC superscalar microprocessor

Describes a CISC superscalar microprocessor. It executes 126 instructions with 14 addressing modes, which include floating-point processing fully compatible with the ANSI/IEEE 754-1985 standard. A

The approach to multiple instruction execution in the GMICRO/400 processor

This paper describes the instruction execution mechanism of the 32-bit microprocessor GMICRO/400 that executes more than one operation per clock cycle and utilizes both superscalar and VLIW design techniques.

A 100 MHz superscalar PA-RISC CPU/coprocessor chip

A RISC CPU chip has been designed for 100-MHz operation and adapted from an earlier CPU designed for 66 MHz in a 1- mu m-gate process, which yielded the desired performance.

An optimizing C compiler for the GMICRO/500 microprocessor

These optimization techniques are described with emphasis on the implementation strategy of the GMICRO/500-specific superscalar optimization, which gave a good basis for the effective improvement of hardware/software performance.

A three-million-transistor microprocessor

  • F. Abu-NofalR. Avra L. Youngs
  • Computer Science
    1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers
  • 1992
Describes a RISC (reduced-instruction-set computer) BiCMOS superscalar microprocessor containing 3.1 M transistors which executes up to three instructions per clock cycle. Clock frequency is 40 MHz

A 200-MHz 64-bit Dual-Issue CMOS Microprocessor

A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede