The GNU 64-bit PL8 compiler: Toward an open standard environment for firmware development

@article{Gellerich2004TheG6,
  title={The GNU 64-bit PL8 compiler: Toward an open standard environment for firmware development},
  author={Wolfgang Gellerich and Torsten Hendel and Rudolf Land and Helge Lehmann and Michael J. Mueller and Peter H. Oden and Hartmut Penner},
  journal={IBM J. Res. Dev.},
  year={2004},
  volume={48},
  pages={543-556}
}
For two decades, large parts of zSeries® firmware have been Written in the PL8 programming language. The existence of a large amount of mature zSeries firmware source code and our excellent experienee with PL8 for system programming suggest keeping this language. However, the firmware address space of today's, zSeries servers may exceed 2 GB, raising the need for a new 64-bit PL8 compiler, since the original implementation, developed at the IBM Thomas J. Watson Research Center, Yorktown Heihts… 
5 Citations

Figures and Tables from this paper

Contributions to the GNU Compiler Collection

Several of IBM's contributions to the GCC compiler are reviewed, including a code generator for the IBM zSeries® processor and a front end for a PL/I-like language used for systems software programming.

Open-standard development environment for IBM System z9 host firmware

To improve code performance, development efficiency, and regression testing, and to develop base functionality for important System z9 features such as enhanced driver maintenance, the development environment has been moved to a fully open-standard development environment.

Advanced firmware verification using a code simulator for the IBM System z9

To verify correct implementation of the z/ArchitectureTM, a new test-case framework is introduced called the Verification Interface for System Architecture, or VISA, which is used in simulations as well as on the actual system.

IBM System z10 firmware simulation

Three new techniques are described: an enhanced static code analysis tool, code coverage, and simulation improvements for the IBM System z10™ platform.

Portable Bit Fields in packetC

The packetC language is built around a packet processing model that involves triggering a parallel copy of a program after the host system assembles the entire packet in a byte array, locates standard protocols within that packet and saves protocol location information.

References

SHOWING 1-10 OF 23 REFERENCES

Porting GCC to the IBM S/390 platform

This paper shares how GCC managed to handle certain architecture features that were difficult or impossible to model in GCC’s architecture-independent framework and points out areas that promise room for further improvement in the back end itself and suggest middle-end modifications that would benefit the platform in particular.

z/CECSIM: An efficient and comprehensive microcode simulator for the IBM eServer z900

For the development of the z900, a new microcode simulator, the z/CECSIM (Central Electronic Complex Simulator), was successfully implemented, thereby allowing an unprecedented amount of development, integration, and testing without the use of engineering hardware.

An overview of the PL.8 compiler

The PL.8 compiler accepts multiple source languages and produces high quality object code for several different machines through global optimization and register allocation.

Millicode in an IBM zSeries processor

This paper is a review of millicode on previous zSeries CMOS systems and also describes enhancements made to the z990 system for processing of the millicodes.

Where Does GOTO Go to?

It turned out that about 99% of all examined files do not contain any GOTO, but it was found that “spaghetti code” was found, generally justified by efficiency arguments.

Program optimization

This paper addresses the problems encountered in launching and promoting a program optimization service in an open shop environment among users with widely varying levels of programming to indicate the method used to isolate and correct the sections of code that preempt the vital computer resources.

Multiple-logical-channel subsystems: Increasing zSeries I/O scalability and connectivity

Improvements to the MCSS I/O measurement facility necessary to facilitate autonomic computing are discussed and an overview of the z990 MCSS architecture is presented.

High Level Microprogramming in I370

Hardware is used for the implementation of the performance critical S/370 instructions and microcode for the remainder of the S/ 370 functions.