The Effect of Interconnect Design on the Performance of Large L 2 Caches

@inproceedings{MuralimanoharTheEO,
  title={The Effect of Interconnect Design on the Performance of Large L 2 Caches},
  author={Naveen Muralimanohar and Rajeev Balasubramonian}
}
The ever increasing sizes of on-chip caches and the growing domination of wire delay have changed the traditional design approach of the memory hierarchy. Many recent proposals advocate splitting the cache into a large number of banks and employ an on-chip network to allow fast access to nearby banks (referred to as Non-Uniform Cache Architectures (NUCA… CONTINUE READING