The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware

  title={The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware},
  author={Qijing Huang and Ruolong Lian and Andrew Canis and Jongsok Choi and R. Xi and Nazanin Calagar and S. Brown and J. Anderson},
  journal={ACM Trans. Reconfigurable Technol. Syst.},
We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated field-programmable gate array (FPGA) hardware. Using an HLS tool implemented within the state-of-the-art LLVM compiler, we study the effect of compiler optimizations on the hardware metrics of circuit area, execution cycles, FMax, and wall-clock time. We evaluate 56 different compiler optimizations implemented within LLVM and show that some optimizations significantly affect hardware quality… Expand
37 Citations
Rapid circuit-specific inlining tuning for FPGA high-level synthesis
  • 2
  • Highly Influenced
Application-Specific Arithmetic in High-Level Synthesis Tools
  • 1
  • PDF
A Survey on Performance Optimization of High-Level Synthesis Tools
  • 1
Automated Synthesis of Streaming Transfer Level Hardware Designs
  • 1
Source-level instrumentation for in-system debug of high-level synthesis designs for FPGA
  • 1
Restructuring Software Code for High-Level Synthesis using a Graph-based Approach Targeting FPGAs
  • PDF
Improving OpenCL Performance by Specializing Compiler Phase Selection and Ordering
  • PDF
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows
  • 4
  • PDF
Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs
  • 7


Trace Scheduling: A Technique for Global Microcode Compaction
  • J. Fisher
  • Computer Science
  • IEEE Transactions on Computers
  • 1981
  • 1,331
  • Highly Influential
  • PDF