The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware

@article{Huang2015TheEO,
  title={The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware},
  author={Qijing Huang and Ruolong Lian and Andrew Canis and Jongsok Choi and R. Xi and Nazanin Calagar and S. Brown and J. Anderson},
  journal={ACM Trans. Reconfigurable Technol. Syst.},
  year={2015},
  volume={8},
  pages={14:1-14:26}
}
We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated field-programmable gate array (FPGA) hardware. Using an HLS tool implemented within the state-of-the-art LLVM compiler, we study the effect of compiler optimizations on the hardware metrics of circuit area, execution cycles, FMax, and wall-clock time. We evaluate 56 different compiler optimizations implemented within LLVM and show that some optimizations significantly affect hardware quality… Expand
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