The Design of TSC Error C/D Circuits for SEC/DED Codes

@article{Gaitanis1988TheDO,
  title={The Design of TSC Error C/D Circuits for SEC/DED Codes},
  author={Nikolaos Gaitanis},
  journal={IEEE Trans. Computers},
  year={1988},
  volume={37},
  pages={258-265}
}
A new design technique for totally self-checking (TSC) error correcting/detecting (C/D) circuits of single error correcting, double error detecting (SEC/DED) codes is described. The structure of these circuits achieves concurrent fault detection and location under normal input conditions. A separate internal fault (IF) indication is provided. This improves the reliability, maintainability, and availability of the entire fault-tolerant system because faults are detected and repaired before the… CONTINUE READING
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Self-testing embedded parity trees,

  • J. Khakbaz
  • in Dig. 14th Annu. Int. Syrnp. Fault-Tolerant…
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