The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4

@article{Gonzalez2018The2P,
  title={The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4},
  author={Christopher J. Gonzalez and Michael A. Floyd and Eric Fluhr and Phillip Restle and Daniel M. Dreps and Michael A. Sperling and Rahul M. Rao and David Hogenmiller and Christos Vezyrtis and Pierce I-Jen Chuang and Daniel Lewis and Ricardo Escobar and Vinod Ramadurai and Ryan Kruse and Juergen Pille and Ryan Nett and Pawel Owczarczyk and Joshua Friedrich and Jose Paredes and Timothy Diemoz and S. K. M. Azizul Islam and Donald W. Plass and Paul Muench},
  journal={IEEE Journal of Solid-State Circuits},
  year={2018},
  volume={53},
  pages={91-101}
}
The POWER9TM family of chips is fabricated in 14-nm silicon-on-insulator finFET technology using 17 levels of copper interconnect. The 695-mm2 24-core microprocessor features a new core based on an execution slice microarchitecture. The chip contains 8 billion transistors and has 120 MB of eDRAM L3 cache. The processor features an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors that direct a digital phase-locked… CONTINUE READING
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POWER8: A 12-core server-class processor in 22 nm SOI with 7.6 Tb/s off-chip bandwidth

  • E. Fluhr
  • IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig…
  • 2014
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