The 1st Level & 2nd Level Solder Joint Reliability Co-design for Larger Die Flip Chip Package

Abstract

This work focuses on co-design of the 1st level and 2nd level solder joint reliability analysis of a flip chip package, with large die. Model with all the layered structures for the build up substrate is compared with the compact model of equivalent substrate. Two 1st level solder bumps are modeled along with the 2nd level solder balls. The fatigue life of… (More)

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