Testing compilers for programmable switches through switch hardware simulation

@article{Wong2020TestingCF,
  title={Testing compilers for programmable switches through switch hardware simulation},
  author={Michael D. Wong and Aatish Kishan Varma and Anirudh Sivaraman},
  journal={Proceedings of the 16th International Conference on emerging Networking EXperiments and Technologies},
  year={2020}
}
Programmable switches have emerged as powerful and flexible alternatives to fixed-function forwarding devices. But because of the unique hardware constraints of network switches, the design and implementation of compilers targeting these devices is tedious and error-prone. Despite the important role that compilers play in software development, there is a dearth of tools for testing compilers for programmable network devices. We present Druzhba, a programmable switch simulator used for testing… 
1 Citations

Figures and Tables from this paper

Switch Code Generation Using Program Synthesis

This paper presents a compiler, Chipmunk, which formulates code generation as a program synthesis problem, and develops a new domain-specific synthesis technique, slicing, which reduces compile times by 1-387x and 51x on average.

References

SHOWING 1-10 OF 31 REFERENCES

Switch Code Generation Using Program Synthesis

This paper presents a compiler, Chipmunk, which formulates code generation as a program synthesis problem, and develops a new domain-specific synthesis technique, slicing, which reduces compile times by 1-387x and 51x on average.

Autogenerating Fast Packet-Processing Code Using Program Synthesis

This work applies program synthesis to build a code generator, Chipmunk, for a simulator of the protocol-independent switch architecture (PISA), which generates code for many programs that a previous code generator based on classical compiler optimizations rejects and uses much fewer hardware resources.

PFPSim: A programmable forwarding plane simulator

  • S. AbdiUmair Aftab Eric Tremblay
  • Computer Science
    2016 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)
  • 2016
PFPSim is introduced, a host-compiled simulator for early validation and analysis of packet processing applications on programmable forwarding plane architectures and can be used as a virtual prototype to simulate and debug their applications before hardware availability.

Lyra: A Cross-Platform Language and Compiler for Data Plane Programming on Heterogeneous ASICs

Lyra is presented, the first cross-platform, high-level language & compiler system that aids the programmers in programming data planes efficiently and not only generates runnable real-world programs, but also uses up to 87.5% fewer hardware resources and up to 78% fewer lines of code than human-written programs.

Gallium: Automated Software Middlebox Offloading to Programmable Switches

Gallium is designed and implemented, a compiler that transforms an input software middlebox into two parts---a P4 program that runs on a programmable switch and an x86 non-offloaded program that Runs on a regular middlebox server.

Learning to Prioritize Test Programs for Compiler Testing

The idea of learning to test is proposed, which learns the characteristics of bug-revealing test programs from previous test programs that triggered bugs, an approach to prioritizing test programs for compiler testing acceleration.

Language-Directed Hardware Design for Network Performance Monitoring

A performance query language, Marple, modeled on familiar functional constructs like map, filter, groupby, and zip is presented, backed by a new programmable key-value store primitive on switch hardware.

p4pktgen: Automated Test Case Generation for P4 Programs

With the rise of programmable network switches, network infrastructure is becoming more flexible and more capable than ever before. Programming languages such as P4 lower the barrier for changing the

p4v: practical verification for programmable data planes

The design and implementation of p4v is presented, a practical tool for verifying data planes described using the P4 programming language that adds several key innovations including a novel mechanism for incorporating assumptions about the control plane and domain-specific optimizations which are needed to scale to large programs.

Packet Transactions: High-Level Programming for Line-Rate Switches

This paper introduces the notion of a packet transaction: a sequential packet-processing code block that is atomic and isolated from other such code blocks that can run at line rate on emerging programmable line-rate switching chips.