Testing a high density logic masterslice

@article{Lowden1979TestingAH,
  title={Testing a high density logic masterslice},
  author={R. Lowden},
  journal={1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={1979},
  volume={XXII},
  pages={250-251}
}
  • R. Lowden
  • Published 1979
  • Engineering
  • 1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
Testing strategy for high density logic in a manufacturing environment will be covered. The approach is applicable to all wiring personalities of a T2L gate logic masterslice. 
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LSI chip design for testability