Testing Superconductor Logic Integrated Circuits

Abstract

——Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits. Index Terms—— Fault modelling, Design-for-Test, Defect Monitor Structures, ATPG

Extracted Key Phrases

8 Figures and Tables

Cite this paper

@inproceedings{Joseph2011TestingSL, title={Testing Superconductor Logic Integrated Circuits}, author={Arun A. Joseph and Hans G. Kerkhoff}, year={2011} }