Testing Circuit-Partitioned 3D IC Designs

  title={Testing Circuit-Partitioned 3D IC Designs},
  author={Dean L. Lewis and Hsien-Hsin S. Lee},
  journal={2009 IEEE Computer Society Annual Symposium on VLSI},
3D integration is an emerging technology that allows for the vertical stacking of multiple silicon die. These stacked die are tightly integrated with through-silicon vias and promise significant power and area reductions by replacing long global wires with short vertical connections. This technology necessitates that neighboring logical blocks exist on different layers in the stack. However, such functional partitions disable intra-chip communication pre-bond and thus disrupt traditional test… CONTINUE READING
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