Testing 3D chips containing through-silicon vias

  title={Testing 3D chips containing through-silicon vias},
  author={Erik Jan Marinissen and Yervant Zorian},
  journal={2009 International Test Conference},
Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test… CONTINUE READING
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