Testability-driven High-level Synthesis

  title={Testability-driven High-level Synthesis},
  author={Zebo Peng},
This paper describes a new approach to integrate testability consideration into high-level synthesis. The approach is based on an iterative technique for high-level synthesis which utilizes a sequence of design-improvement transformations to generate a register-transfer level design from a VHDL behavioral specification. A testability analysis algorithm is used to analyze the intermediate results of the transformation process. Based on the analysis results, appropriate testability-improvement… CONTINUE READING


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