Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs

@article{Noia2009TestwrapperOF,
  title={Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs},
  author={Brandon Noia and Krishnendu Chakrabarty and Yuan Xie},
  journal={2009 IEEE International Conference on Computer Design},
  year={2009},
  pages={70-77}
}
System-on-chip (SOC) designs comprised of a number of embedded cores are widespread in today's integrated circuits. Embedded core-based design is likely to be equally popular for three-dimensional integrated circuits (3D ICs), the manufacture of which has become feasible in recent years. 3D integration offers a number of advantages over traditional two-dimensional (2D) technologies, such as the reduction in the average interconnect length, higher performance, lower interconnect power… CONTINUE READING
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Test architecture design and optimization for three-dimensional SoCs

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