• Engineering
  • Published 2010

Test time optimization in scan circuits

@inproceedings{Shanmugasundaram2010TestTO,
  title={Test time optimization in scan circuits},
  author={Priyadharshini Shanmugasundaram},
  year={2010}
}
As circuit sizes increase with scale down in technology, the time required to test the circuits also increases. Expensive automatic test equipment (ATE) is used to test these circuits and the cost of testing becomes a significant fraction of the total cost of the chip. Testing cost of a chip is directly related to the time its testing takes. However, test time cannot be reduced by simply applying the tests at a faster speed because if the test clock frequency is increased, the power consumed… CONTINUE READING

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