Test set compaction algorithms for combinational circuits

@article{Hamzaoglu1998TestSC,
  title={Test set compaction algorithms for combinational circuits},
  author={I. Hamzaoglu and J. Patel},
  journal={1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)},
  year={1998},
  pages={283-289}
}
  • I. Hamzaoglu, J. Patel
  • Published 1998
  • Engineering
  • 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)
This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating the minimum single stuck at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated… Expand

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An advanced automatic test pattern generation system for combinational circuits, called MinTest, which found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan versions of theISCAS89 benchmark circuits. Expand
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