Test generation in VLSI circuits for crosstalk noise

  title={Test generation in VLSI circuits for crosstalk noise},
  author={Weiyu Chen and Sandeep Kumar Gupta and Melvin A. Breuer},
  journal={Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)},
  • Weiyu ChenS. GuptaM. Breuer
  • Published 18 October 1998
  • Computer Science
  • Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. [] Key Method Our modeling technique captures such properties as the amplitude of a pulse and its rise/fall times and the delay through a device. To expedite the computation of the response of a logic gate to an input pulse, we have developed a novel way of modeling such gates by an equivalent inverter.

Figures and Tables from this paper

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

A mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay is developed.

Analytical models for crosstalk excitation and propagation in VLSI circuits

The authors develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high-speed circuits and present a new way for predicting the output waveform produced by an inverter due to a nonsquare wave pulse at its input.

A BIST Technique for Crosstalk Noise Detection in FPGAs

  • W. Al-AssadiS. Kakarla
  • Physics
    2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
  • 2008
This paper proposes a new approach for detecting effects such as glitches and delays in transition due to crosstalk noise in FPGAs, which is similar to the BIST (built-in self test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosStalk faults without any extra overhead for testing.

Validation and Test Generation for Inductance Induced Noise on VLSI Interconnects

Advancements in integrated circuit technology have led to an increase in switching speeds of digital circuits. This increase is the primary reason why inductance induced noise (e.g., oscillation,

Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays

An automatic test pattern generation solution which uses 0-1 integer linear programming to maximize the cumulative voltage noise at a given victim net because of crosstalk and loading in conjunction with propagating the fault effect to an observation point is presented.

Test generation for crosstalk-induced delay in integrated circuits

A model is presented to evaluate the effect of parasitic coupling crosstalk and conditions for the creation of the worst-case coupling and propagation of a delayed signal are presented.

Timed test generation for crosstalk switch failures in domino CMOS

A timed test generation methodology for CMOS domino circuits is presented that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity creates a noise effect that is propagated within the clock-cycle constraint.

Validation and test generation for oscillatory noise in VLSI interconnects

  • Arani SinhaS. GuptaM. Breuer
  • Computer Science
    1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)
  • 1999
This work presents an algorithm for generating vectors for validation and manufacturing test to detect logic-value errors caused by inductance induced oscillation, and derived analytical expressions, as functions of rise and fall times for the magnitude of overshoots and undershoots.

Built-in Self-Test for crosstalk faults in a digital VLSI

A Built-In Self-Test (BIST) method which can detect the crosstalk faults and can be realized by a relatively small area overhead; by adopting a circuit configuration during simulation which is different from the one during test, the simulation time is shortened and testing of large-scale circuits has been made possible.

Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults

A novel solution that combines 0-1 integer linear program (ILP) with traditional stuck-at fault ATPG is presented, formulated as a linear programming problem while the fault effect propagation is treated as an ATPG problem.



Automatic test pattern generation for crosstalk glitches in digital circuits

An efficient methodology for generating test vectors to detect crosstalk glitch effects in digital circuits with ATEG (Automatic Test Extractor for Glitch) algorithm, which uses the multiple backrace technique and uses a "forward-evaluation" technique in its backtacking phase.

Crosstalk reduction for VLSI

An expression for the coupled noise integral and a bound for the peak coupled noise voltage are derived which shows order of magnitude improvements in both accuracy and fidelity compared to the charge sharing model used in previous work.

CMOS Circuit Speed and Buffer Optimization

An improved timing model for CMOS combinational logic is presented, which yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform.

Inverter models of CMOS gates for supply current and delay evaluation

The reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits, is presented, applicable to dynamic logic gates as well.

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

This paper presents a logic level characterization and fault model for crosstalk faults and shows how a fault list of such faults can be generated from the layout data, and gives an automatic test pattern generation procedure for them.

An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation

A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed and shows that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation.

Delay analysis of series-connected MOSFET circuits

In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay

Methods to improve digital MOS macromodel accuracy

This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the

Process aggravated noise (PAN): new validation and test problems

  • M. BreuerS. Gupta
  • Engineering
    Proceedings International Test Conference 1996. Test and Design Validity
  • 1996
The need for automating the process of selecting design corners as well as test sequences for validation and outline strategies for their automation is demonstrated.

Analytical transient response of CMOS inverters

A one-dimensional function dependence of the inverter propagation delay and output slew rate on circuit parameters is derived and an inverter macromodel for timing analysis is suggested and experimentally verified.