Test cost reduction using partitioned grid random access scan

@article{Baik2006TestCR,
  title={Test cost reduction using partitioned grid random access scan},
  author={Dong Hyun Baik and Kewal K. Saluja},
  journal={19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)},
  year={2006},
  pages={6 pp.-}
}
The random access scan (RAS) has the ability to address major problems associated with serial-scan method. A practically implementable RAS test architecture called progressive random access scan (PRAS) was introduced earlier. This paper proposes a generalized architecture for the PRAS. We show that the generalized PRAS architecture offers two orders of magnitude gains in test application time over traditional serial scan and is superior to multiple serial scan in terms of the use of tester… CONTINUE READING

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References

Publications referenced by this paper.
Showing 1-10 of 20 references

Cocktail scan based on random access scan toward low power and high efficiency test

L S.-P.
Proc. Int. Conf. Computer Aided Design, 2005. Accepted and to appear, also available from the authors. • 2005
View 1 Excerpt

On low-capture-power test generation for scan testing

23rd IEEE VLSI Test Symposium (VTS'05) • 2005
View 1 Excerpt

Circularscan: a scan architecture for test cost reduction

Proceedings Design, Automation and Test in Europe Conference and Exhibition • 2004
View 2 Excerpts

Embedded deterministic test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2004
View 3 Excerpts

Random access scan: a solution to test power, test data volume and test time

17th International Conference on VLSI Design. Proceedings. • 2004
View 4 Excerpts

Test cost reduction through a reconfigurable scan architecture

2004 International Conferce on Test • 2004
View 2 Excerpts

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