Test cost reduction using partitioned grid random access scan

  title={Test cost reduction using partitioned grid random access scan},
  author={Dong Hyun Baik and Kewal K. Saluja},
  journal={19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)},
  pages={6 pp.-}
The random access scan (RAS) has the ability to address major problems associated with serial-scan method. A practically implementable RAS test architecture called progressive random access scan (PRAS) was introduced earlier. This paper proposes a generalized architecture for the PRAS. We show that the generalized PRAS architecture offers two orders of magnitude gains in test application time over traditional serial scan and is superior to multiple serial scan in terms of the use of tester… CONTINUE READING

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