Test cost reduction for SOCs using virtual TAMs and lagrange multipliers

  title={Test cost reduction for SOCs using virtual TAMs and lagrange multipliers},
  author={Anuja Sehgal and Vikram Iyengar and Mark D. Krasniewski and Krishnendu Chakrabarty},
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching high speed ATE channels to slower scan chains… CONTINUE READING
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