Test control for secure scan designs

  title={Test control for secure scan designs},
  author={David H{\'e}ly and Fr{\'e}d{\'e}ric Bancel and Marie-Lise Flottes and Bruno Rouzeyre},
  journal={European Test Symposium (ETS'05)},
Designing secure ICs requires fulfilling many design rules in order to protect access to secret data. However, these security design requirements may be in opposition to test needs and testability improvement techniques that increase both observability and controllability. Nevertheless, secure chip designers cannot neglect the testability of their chip; a high quality production testing is primordial to ensure a good level of security since any faulty devices could induce major security… CONTINUE READING
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