Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences

@article{Pomeranz2002TestCF,
  title={Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences},
  author={Irith Pomeranz and Sudhakar M. Reddy},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={2002},
  volume={21},
  pages={706-714}
}
We propose a procedure for generating compact test sets with enhanced at-speed testing capabilities for scan circuits. Compaction refers here to a reduction in the test application time, while at-speed testing refers to the application of primary input sequences that contribute to the detection of delay defects. The proposed procedure generates an initial test set that has a low test application time and consists of long sequences of primary input vectors applied consecutively. To construct… CONTINUE READING

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