Test chip for the development and evaluation of test structures for measuring stress in metal interconnect

@article{Terry2004TestCF,
  title={Test chip for the development and evaluation of test structures for measuring stress in metal interconnect},
  author={J. G. Terry and Stewart Smith and A. J. Walton and A. Gundlach and J. T. M. Stevenson and A. B. Horsfall and Kang Wang and J.M.M. dos Santos and S. M. Soare and N. G. Wright and A. G. O'Neill and S. Bull},
  journal={Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516)},
  year={2004},
  pages={69-73}
}
The development of a new test chip is presented, which contains the first test devices able to directly measure stress in metallic interconnect layers associated with silicon IC technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip has been used to fabricate working devices allowing the study of stresses in aluminium layers before and after sample sintering. The results are presented along with the design… CONTINUE READING