Test chip characterization of X architecture diagonal lines for SoC design

@article{Arora2004TestCC,
  title={Test chip characterization of X architecture diagonal lines for SoC design},
  author={N. D. Arora and Liqun Song and S. Shah and Komal Naik Joshi and Kalyan Thumaty and Aki Fujimura and J. P. Schoellkopf and Hugues Brut and Mike Smayling and Toshi Nagata},
  journal={Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516)},
  year={2004},
  pages={75-79}
}
This paper addresses the manufacturability, yield and reliability aspects of an X architecture (diagonal lines) silicon-on-chip (SoC) design that enables IC chips to become faster and smaller (area) compared to the same design in a Manhattan structure. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both a 130 nm and a 90 nm copper CMOS processes. The measurements of the line resistance (Kelvin… CONTINUE READING
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