Test-access mechanism optimization for core-based three-dimensional SOCs

@article{Wu2008TestaccessMO,
  title={Test-access mechanism optimization for core-based three-dimensional SOCs},
  author={Xiaoxia Wu and Yibo Chen and Krishnendu Chakrabarty and Yuan Xie},
  journal={2008 IEEE International Conference on Computer Design},
  year={2008},
  pages={212-218}
}
Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. We present an optimization technique… CONTINUE READING
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