Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture

@inproceedings{Bailey2002TestMF,
  title={Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture},
  author={B. Bailey and A. Metayer and B. Svrcek and Nandu Tendolkar and E. Wolf and Eric Fiene and Mike Alexander and Rick Woltenberg and Rajesh Raina},
  booktitle={ITC},
  year={2002}
}
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