Test Generation for Precise Interrupts on Out-of-Order Microprocessors

  title={Test Generation for Precise Interrupts on Out-of-Order Microprocessors},
  author={Padmaraj Singh and David L. Landis and Narayanan Vijaykrishnan},
  journal={2009 10th International Workshop on Microprocessor Test and Verification},
Validation of precise interrupts on a modern pipelined processor is a non-trivial task. The common approach of asserting external interrupts at random test points offers insufficient coverage, and exhaustive simulation under all pipeline conditions is grossly impractical. This paper describes an enhanced technique for effective verification of a pipelined processor in the event of external interrupts. The paper develops a framework to identify critical points in a test program when resource… CONTINUE READING